The present invention relates to the communication control technology and, particularly, to the technique which is effectively applied to the serial data communication among microprocessors, e.g., effectively applied to communication control units used in a local area network.
For carrying out the serial data communication among microprocessors, there are provided communication LSIs such as type .mu.PD7201A manufactured by Nippon Electric Co., Ltd. FIG. 5 shows an example of systems using the communication LSI .mu.PD7201A. The microprocessor has its CPU connected through a system bus (BUS) with a memory (MEM), DMA controller (DMAC) and serial communication LSI (SIO).
In this system, when the CPU intends to transmit data to another microprocessor (not shown), the CPU sends a transfer start command to the DMA control (DMAC). The DMA controller (DMAC) responds to the transfer request signal from the communication LSI (SIO) to provide the address on the system bus (BUS), read out the intended transmission data from the memory (MEM) and delivers it to the communication LSI (SIO). The transmission data supplied to the communication LSI (SIO) is stored temporarily in the internal FIFO and, after being converted into serial data, it is sent to the external microprocessor.
When the communication LSI (SIO) has received data from outside, it is converted into bytewise parallel data and stored in a receiving FIFO. After receiving notification of the received data, the CPU issues a transfer start command to the DMA controller (DMAC), and the DMAC responds to the transfer request signal from the communication LSI (SIO) to transfer the received data in the FIFO to the memory (MEM). Thereafter, the CPU makes access to the memory (MEM) to fetch the received data. (Refer to "NEC Electronic Device .mu.PD7201A User's Manual" published in 1984 by Nippon Electric Co., Ltd.)
In the above-mentioned system, the SIO and DMAC operate independently. For example, when the SIO has received data, it signals the CPU, and then the CPU issues a command to the DMAC so that DMA transfer is started. Upon receiving a frame of data, the SIO informs the CPU, which then directs the DMAC to halt. Similarly, at transmission, starting and ending of data transfer is sent to the CPU, and the SIO and DMAC are controlled independently on the CPU command level.
Accordingly, the conventional system needs CPU intervention at each transmission or reception of frame data, and this results in an excessive load to the CPU and a slower protocol processing.